Evolutionary Leap In Embedded Design System-level Programmability-kisstudou

.puters-and-Technology How many embedded projects have you worked on that successfully transitioned between lifecycle phases of the project without major rework of system designs, bill of materials, layouts, etc.? If youre answer is less than 100%, as the majority of the embedded world is, then you should open your mind to a new methodology to embedded design that will save you countless hours, dollars and headaches. In this article well explore the embedded design challenges you face on a day-today basis and, in a pragmatic manner, how you can over.e with true system-level programmability. First, lets briefly look at what I mean by true system-level programmability. True System-Level Programmability Lets break this apart into three sections and describe each, from right-to-left: Programmability, System-Level, and True. Programmability is not to be confused with configurability; but rather is the ability to build a function using basic building blocks. In this context, these basic building blocks are implemented in hardware and are used together to build a function by means of configuring registers, data-paths and signal-paths. For example, figure 1 below describes the basic building blocks within Cypresss next generation PSoC device architectures, PSoC 3 and PSoC 5, for implementing true system-level programmability. These basic building blocks, as highlighted in the figure, consist of a high performance 8-bit 8051 (PSoC 3) or 32-bit ARM Cortex M-3 (PSoC 5) processor, a programmable clocking tree, Universal Digital Blocks (UDBs), programmable analog blocks and programmable routing and interconnects (analog, digital and system buses). PSoC 3 Architecture The clocking system of the PSoC 3 and PSoC 5 architectures enables a programmable set of analog and digital clocks to support a variety of peripherals like ADCs, PWMs, counters, etc. With eight individually sourced 16-bit clock dividers for the digital system peripherals and four individually sourced 16-bit clock dividers for the analog system peripherals all reaching back to a set of four internal or two external clock sources; you have a powerful clocking tree. A UDB is very powerful, flexible digital logic block. Each UDB in the PSoC 3 and PSoC 5 architectures contain an ALU-based 8-bit datapath, two fine grained PLDs, a control and status module as well as a clock and reset module. These elements can be .bined to perform the function of a low-end microcontroller, they can be chained together with other UDBs to enable larger functions, or they can implement digital peripherals such as timers, counters, PWMs, UARTs, I2C, SPI, CRCs, etc. With 24 UDBs in some PSoC 3 and PSoC 5 families of devices, you can even implement a 24-core processor in addition to the 8051 or ARM Cortex-M3 processors, or the internal DMAa very powerful architecture. The analog capabilities of PSoC 3 and PSoC 5 .bine high-precision fixed-function analog (reference voltage accurate to +/- 0.1% over industrial temperature and voltage ranges) with a set of programmable analog peripherals that can be used to implement: mixers, trans-impedance amplifiers, buffers, op-amps, and more. The .bination of flexible, high-precision analog capabilities opens up many possibilities for unique, powerful designs. Finally, the routing and interconnect of the PSoC 3 and PSoC 5 architecture, as you can see above in figure 1, is made up of system buses that enable any GPIO to be digital, analog, CapSense, or LCD drive I/Oa truly powerful feature that can offer significant cost savings (4-layer to 2-layer PCBs) and easier board layout with true routing freedom. So, what does system-level mean? We have long had .ponent-level programmability in the form of programmable digital logic (CPLDs, FPGAs, etc.), programmable analog (switched-capacitor and similar functions), programmable clocks, programmable processors, etc. What system-level programmability means is simply all of these programmable .ponents in a single platform, a single device all controlled and configured via an easy to use, hierarchical schematic-based, software development environment. Figure 2 shows a system-level view of a brushless DC Motor control example application. As you can see in this figure, you dont need to worry about the details of how these individual .ponents are instantiated; instead you focus on what you want these peripheral functions to do. Whether its taking tachometer, temperature or pump pressure readings to provide a feedback loop to the motor control function, or driving the 3-phase motor using individual PWM controls, you can solve your system design challenges without worrying about the low-level details of which discrete ICs or peripheral .ponents to use. Pragmatic Application of System-Level Programmability to Solve Embedded Design Challenges You face a number of embedded design challenges. First is adapting to changechanges to requirements, layouts, designs, availability of materials, etc. Next is getting to market fastbeating the .petition and releasing a product at the right time to net the most impact. Another challenge is analog .plexitieschoosing, configuring and using the right parts for the right purposes. Finally you must protect your design IP to prohibit .petitors from replicating your designs and stealing your market share. Cypresss PSoC programmable system-on-chip and development software have been designed to meet these challenges head-on and in this section were going to take a pragmatic approach to how true system-level programmability and PSoC addresses these challenges. Adapting to Change The only constant in the life of an embedded engineer is change, and your ability to embrace change by planning for it and using tools that empower you to adapt is the only way you can truly be successful. As you saw in figure 2, a change to a PSoC engineer could mean a simple modification of a peripheralperhaps increasing an ADCs resolution (figure 3), or could be as .plicated as adding additional functionality into a design, like a control interface via USB or an LCD Segment Display and capacitive sensing buttons (figure 4). With true system-level programmability you can embrace change and use it to develop the best products you can imagine. Getting to Market Fast The biggest challenge in getting to market fast is not always concepts or ideas, but in creating a product from these ideas. Quickly getting a product to market can earn you higher margins and a more focused market with less .petition. PsoC engineering enables rapid-prototyping of a solution with easy in-chip tweaking and programming along with a system-level software development environment. With these two capabilities, you can easily breadboard a hardware solution to understand the true requirements and get your product into production. Analog .plexities The PSoC programmable system-on-chip platform and its software development environment ease the use of analog circuitry and functions through its intuitive system-level, schematic-based design methodology. As you saw in figures 2 and 3, for example, the instantiation of analog peripherals is as simple as a drag-and-drop of the .ponent on to the design canvas in PSoC Creator followed by peripheral configuration settings specific to the function youre implementingfor the ADC in this example: resolution, conversion rates, clock sources, etc. The instantiation of other analog peripherals like trans-impedance amplifiers, filters, analog multiplexers, .parators, DACs and other peripherals is just as simple. Protection of Design IP The PSoC programmable system-on-chip provides an additional layer of security by way of its system-level programmability thats embedded in the device. If .petitors examine the die, all they can see are the .ponents that make up the PsoC device itself and not the firmware that initializes and instantiates the system you developed using PSoC Creator. The firmware stored in the PSoC devices is also protected with several degrees of protection and defined by memory block to ac.modate several levels of protection across the entire device: no protection (used during development), external read protection, external read/write protection as well as full protection (no external read/write or internal write). With these protection levels,the secret sauce of your designs when implemented in the PSoC device can easily be protected from standard reverse engineering techniques. About the Author: 相关的主题文章: